Sigma-delta analog-to-digital converters (ADCs) represent a popular choice for a wide range of analog-to-digital conversion applications, including precision industrial and scientific applications, and in digital signal processing applications, such as within digital communication transceivers. Their advantages include increasing viability with continuing advances in integrated circuit technology, and the ability to shift quantization noise well outside the frequency range of interest.
FIG. 1 illustrates a simple example of a first-order sigma-delta analog-to-digital converter (ADC) 10 according to a known arrangement, which includes a loop filter 12, a quantizer 14, a decimation filter 16, and a digital-to-analog converter (DAC) 18. According to well known operation, the loop filter 12 receives an analog input signal u, combines it with an analog conversion feedback signal va, and generates a corresponding loop filter output signal y. In turn, quantizer 14—here, shown as a single-bit quantizer-outputs a digital value, e.g., 1 or 0, indicating whether the loop filter output signal y is above or below a reference value. For example, the reference value for the quantizer 14 is 0, so it outputs a digital 1 if its input is positive and a digital 0 if its input is negative. The digital stream, vd, output by the quantizer 14 drives the DAC 18, which converts the digital feedback into the aforementioned (analog) conversion feedback signal va.
FIG. 2 offers additional details for the ADC 10, wherein the loop filter 12 includes a single integrating amplifier 20 having an input signal resistance 22 and a feedback capacitor 24. The quantizer 14 includes an n-bit quantization circuit 26 that compares its input signal to a reference signal at time instants driven by an applied clock signal. Of more interest, the DAC 18 is configured as a switched current source and includes a resistor 30 in the conversion feedback path, which is switchably coupled through switch 32 to one of a signal reference (e.g., ground) and ±VREF. The 1s and 0s in the digital stream generated by the quantizer 14 drive the switch 32 determine whether +VREF or −VREF is coupled to the loop filter 12 through the resistor 30 in each feedback cycle of the ADC 10.
Therefore, in each feedback cycle, the DAC 18 generates a positive (or negative) current pulse (denoted as an “SI” pulse to indicate the switched current source basis for pulse generation) reflecting the value of the digital bit output by the quantizer 14 for that cycle. It is important that the DAC 18 generates the current pulse consistently in each cycle, such that the same amount of charge is transferred between the DAC 18 and the loop filter 12 in each feedback cycle. The current-source configuration of DAC 18 works well in that regard, with FIG. 3 illustrating an example positive-going current pulse for the conversion feedback signal. However, one sees from the waveform illustration depicted in FIG. 3 that the conversion feedback signal current pulse maintains its full magnitude across the full pulse width, such that at the end of the feedback cycle, time TP, the signal current is still at full magnitude.
With this high-current pulse ending condition, the total amount of charge, Qtot transferred by the DAC 18 in each feedback cycle is dramatically dependent on the pulse width. Any jitter in the feedback cycle clock signal, i.e., jitter in the clock signal that establishes the conversion feedback signal pulse width, can substantially increase or decrease the amount of charge transferred in a given feedback cycle, leading to inaccuracy in the ADC 10.
FIG. 4 illustrates another known arrangement for the sigma-delta ADC 10, which addresses clock jitter sensitivity concerns. Here, the DAC 18 uses a capacitor 34 for charge transfer in each feedback cycle, where the capacitor is charged to ±VREF. In contrast to the DAC configuration of FIG. 1, the configuration here provides for a decreasing conversion feedback signal current, as illustrated in FIG. 5, that decays to some lower threshold, Ir, by time TP. Because the current magnitude of the conversion feedback signal is relatively low at the end of the feedback cycle, the total amount of charge transferred during the feedback cycle does not change much with clock jitter. Unfortunately, relatively high peak currents must be tolerated in this configuration, and the presence of these high peak currents increases DC power consumption, and imposes high gain-bandwidth (GBW) and slew rate requirements on the integrating amplifier 20 in the loop filter 12.
The above examples thus illustrate the use of a current-source based DAC that reduces or eliminates high peak currents but exhibits high sensitivity to clock jitter, and a capacitor-based DAC that exhibits good clock jitter sensitivity but imposes high GBW and slew rate requirements on integrating amplifiers because of its high peak currents, and results in higher DC current consumption. As such, both approaches compromise the design and performance of sigma-delta ADCs.